1. Field of the Invention
This invention concerns a method of manufacturing a semiconductor device, and in particular concerns the improvement of selective vapor growth.
2. Description of the Related Art
In recent years, large-scaled integrated circuits (LSI) have come to be widely used in major parts of computers and communications equipment. These LSI consist of a large number of active elements and passive elements assembled in an integrated fashion on a rectangular substrate of side several mm in length such that they form the components of an electric circuit. Further, the trend is towards increasingly high levels of integration, and intensive research is being carried out to make the elements of such devices even smaller and increase the density of components in an attempt to manufacture super LSI.
In the case of LSI interconnections, for example, design specifications call for smaller size and so the wiring or the interconnection layer is of smaller width; at the same time, the number of active elements is increasing, so the wiring pattern must be finer, longer and more complex. If however aluminum, which is a wiring material, is led directly through contact holes as in ordinary wiring, several problems arise.
Firstly, more defects occur in the openings of such wiring, and electromigration effects due to electric stress are more evident.
Secondly, diffusion regions such as, for example, the source and drain of MOSLSI are tending to become shallower, but if aluminum is brought into contact with such a shallow diffusion region and subjected to heat treatment, mutual diffusion of aluminum and silicon often occurs, and the Al atoms pass through the diffusion region in what is known as a "pit" phenomenon.
Thirdly, the aspect ratio (contact hole depth/contact hole width) of contact holes used to connect the wiring to the diffusion region is increasing, and this leads to more breaks in the wiring in the holes and increased wiring resistance.
Moreover, the second and third problems above are not limited to contacts between the diffusion region and the wiring, but also occur between wiring layers in multi-layer interconnections.
A reliable wiring was therefore required which was not so much affected by these problems.
To solve these problems, methods have been proposed whereby a high melting metal layer such as tungsten (W) is deposited by a selective CVD process on Al wiring, or a high melting metal such as tungsten (W) or aluminum is filled by a selective CVD process in contact holes or via holes. In these selective CVD processes, it is possible to grow a metal layer only within a specified region by suitably choosing the conditions. In the selective CVD of a W film, for example, a gas mixture of a halide such as tungsten hexafluoride (WF.sub.6) and a silane is used as a reactive gas to deposit a W film selectively on the surface of Si, Al or a high melting metal, the W film not being deposited on the surface of an insulating film such as silicon dioxide.
FIG. 1 shows the situation where a high melting metal such as tungsten (W) has been filled in a via hole. In FIG. 1, a first interconnection layer 3 of aluminum is formed on an insulating film 2 deposited on a semiconductor substrate 1. This first interconnection layer 3 extends perpendicularly to the plane of the paper. Reference numeral 4 indicates an inter-layer insulating layer, and W layer 5 is deposited by selective CVD in a via hole formed in layer 4. Reference numeral 6 indicates a second interconnection layer connected to W layer 5. In this structure, there is no step on the upper edge of the via hole, and disconnection of the second interconnection layer in this part is thereby completely prevented.
There are however several problems inherent in this wiring arrangement. As shown in FIG. 2, for example, if a via hole is formed in inter-layer insulating layer 4 so as to expose first interconnection layer 3, an insulating material 7, consisting of natural oxide, or good insulators such as fluoride, carbide, oxide or mixtures of these substances which may be formed for some reason when the via hole is formed, adheres to the exposed surface. It is highly possible that these insulating materials are generated from a resist material or etching gas at the time of patterning. If therefore W is deposited by selective CVD on first interconnection layer 3, it is deposited unevenly wherever such insulating material 7 is thin as shown by deposited material 8, and a perfect layer is not obtained. This is also known to be the reason why the contact resistance between first interconnection layer 3 and second interconnection layer has a fairly high value. Moreover, this insulating material 7 has a low vapor pressure and is extremely stable chemically, so it is very difficult to remove chemically.
To remove insulating material 7, a pre-treatment with dilute fluoric acid is generally carried out, but in the case of the minute via holes and contact holes found in modern high-density integrated circuits, this method does not give a sufficiently low contact resistance. Further, even if this pre-treatment is carried out with dilute fluoric acid, the substrate is exposed to the air until it is inserted in the film deposition apparatus, and a natural oxide film again forms on the exposed surface of first interconnection layer 3.
A physical type of treatment by sputtering with a plasma of an inert gas such as argon, might also be envisaged. With this form of treatment, however, the surface of inter-layer insulating layer 4 is activated, and the selectivity of W in the selective CVD process is impaired. More specifically, as shown in FIG. 3, W is deposited not only on the surface of first interconnection layer 3 but also on the surface of inter-layer insulating layer 4, and a W layer 9 is formed. That is, it is difficult to deposit selectively tungsten only in the via hole. The activation of the surface of insulating layer 4 is thought to be due to the fact that sputtering causes a large number of silicon dangling bonds to project from this surface.
This problem is not limited to selective CVD of a W layer, and occurs also in the case of selective CVD of a polycrystalline layer using SiH.sub.4 as the raw gas, and the selective CVD of an aluminum layer using trimethyl aluminum (Al(CH.sub.3).sub.3) as the raw gas.